1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits and semiconductor devices, and, more particularly, to the formation of semiconductor devices employing an optical planarization layer.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of electronic circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced for forming field effect transistors, wherein, for many types of complex circuitry, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, for example, N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer.
A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed between the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Particularly for transistor devices with very short channel lengths, for example, of some 10 nm, gate structures with high-k dielectric gate insulating layers and one or more metal layers functioning as a gate electrode have been provided that show improved operational characteristics as compared to conventional silicon dioxide/polysilicon gates. The high-k isolation layers may include or consist of tantalum oxide, hafnium oxide, titanium oxide or hafnium silicates, for example.
There are basically two well-known processing methods for forming a planar or 3D transistor with a high-k/metal gate structure: the so-called “gate last” or “replacement gate” technique and the so-called “gate first” technique. In the replacement gate technique, a so-called “dummy” or sacrificial gate structure is initially formed and remains in place as many process operations are performed to form the device, for example, the formation of doped source/drain regions, performing an anneal process to repair damage to the substrate caused by the ion implantation processes and to activate the implanted dopant materials. At some point in the process flow, the sacrificial gate structure is removed to define a gate cavity where the final HK/MG gate structure for the device is formed. Using the “gate first” technique, on the other hand, involves forming a stack of layers of material across the substrate, wherein the stack of materials includes a high-k gate isolation layer, one or more metal layers, a layer of polysilicon, and a protective cap layer, for example, silicon nitride. One or more etching processes are performed to pattern the stack of materials to thereby define the basic gate structures for the transistor devices.
The protective cap layer particularly protects the gate during an embedded silicon/germanium (SiGe) sequence carried out in order to form source and drain regions, etc. Sidewall spacers are usually formed at sidewalls of the patterned gate structure and a sacrificial oxide layer is formed on the sidewall spacers and the wafer surface to protect the sidewall spacers when the protective cap layer is removed in a later processing step. Horizontal portions of the sacrificial oxide layer are removed, thereby exposing the protective cap layer. After completion of the embedded SiGe sequence, the protective cap layer is to be removed in order to ensure stable silicidation of the gate. A metal silicide may typically be formed in the gate electrode, which may comprise polysilicon material, thereby enhancing conductivity and thus reducing signal propagation delay. Although an increased amount of metal silicide in the gate electrode may per se be desirable in view of reducing the overall resistance thereof, a substantially complete silicidation of the polycrystalline silicon material down to the gate dielectric material may not be desirable in view of threshold voltage adjustment of the corresponding transistor element. It may, therefore, be desirable to maintain a certain portion of the doped polysilicon material in direct contact with the gate dielectric material so as to provide well-defined electronic characteristics in the channel region, so as to avoid significant threshold variations, which may be caused by a substantially full silicidation within portions of the gate electrode.
However, during the processing steps of removal of the sacrificial oxide and the protective cap layer, for example, comprising or made of SiN, extended active device areas of the wafer are undesirably affected, i.e., material in large active device regions formed close to the transistor device comprising the protective cap layer in an intermediate state is conventionally removed, resulting in a performance loss of the final semiconductor device.
In view of the situation described above, the present disclosure provides techniques that allow for the formation of a semiconductor device comprising etching of a sacrificial oxide layer (a protective cap layer) formed on a gate of a transistor without significantly attacking an active device area of the semiconductor device.